1. Technical Field
The present invention relates to a method and system for redefinition of permitted transactions and associated responses in a data processing system to avoid delay and cost impact from late specification changes in the design of application specific integrated circuits.
2. Background of the Related Art
In the planning of complex hardware for computer systems or other digital processing equipment; numerous and complex transactions are contemplated in the design of application specific integrated circuits (ASIC), used in the implementation of a system. Such ASIC devices may include memory controllers and other subsystem components designed for a particular data processing system In such data or information processing systems, it is not uncommon that there are late specification changes in the design process which result in system response errors that must be corrected.
For system speed and chip density purposes, system logic is normally formed and manufactured into an ASIC which, once manufactured, may not be altered or changed without going through a redesign process. Such a redesign usually is expensive in terms of retooling and retesting the ASIC. When the ASIC finally reaches post-silicon testing, it may be discovered that a transaction in the system design may not be handled correctly and may stop forward progress of the system development and testing. Such delays cause expense in terms of time to market and add additional development cost because of changes that would be required. There is presently no mechanism to allow simple and effective redefinition of allowed transactions and associated responses within a system so that an ASIC may continue to operate without production changes.
In the past, the problem described was commonly addressed by designers of complex transaction handlers by using various mechanisms. First, configuration bits on one or more internal registers can sometimes be used to change configurations of the system so that problematic transactions or system bugs which arise cannot occur. Using such configuration bits often reduce system performance, limit the features available or usability of the system as a whole.
Other means for addressing this problem has included micro sequencer based transaction handlers. This technique is based on execution of microcode and thus the system can be reprogrammed to handle any of the problematic cases that may arise after post manufacturing. While the solution is versatile, computer systems which use microcode are usually unable to achieve the same clock speeds and logic densities as hard coded logic which is the preferred environment of many systems today.
Also, the problem has been addressed by the implementation of external pin outputs that are connected to the internals of transaction handlers that can be used to change the response of the handler to specific and limited transaction problems. This latter technique of addressing the problem usually requires some ability to view internal transaction handler signals on physical pins introduced externally to the ASIC. This method of addressing the problem allows for the design of external hardware to generate the signals for the external pins. Further, the technique adds pins to the integrated circuit being designed and it is difficult, if not impossible, to provide fill performance at high clock speeds. All of the above current techniques have identified drawbacks which the present invention addresses.